Legacy IAS Academy · Daily PIB Analysis
PIB Analysis — 16 September 2026
3 syllabus-mapped government releases, analysed · scheme anatomy, context and critique · a UPSC-pattern Mains question with every topic
Press Information Bureau
Government of India
In-Depth PIB Analysis3 Items
Core TopicImportantConcise
Economy & InfrastructureGS Paper III
01UPI’s New MDR Framework: What Stays Free, What Is Charged
02Varuna Elevated Corridor, Varanasi
Science & TechnologyGS Paper III
03SEMICON India 2026 & India’s Semiconductor Mission — From the Basics
Economy & InfrastructureGeneral Studies Paper III
01
UPI’s New Merchant Discount Rate Framework — Ending the Blanket Zero-MDR Regime for Large Merchant Payments
A Merchant Discount Rate (MDR) will now apply to about 4% of person-to-merchant UPI payments — those above ₹2,000 — while all person-to-person transfers and small-merchant receipts stay free. It reverses a six-year policy of zero MDR on UPI.
◈ Static Background — From the Basics
A payment system is the set of rules, institutions and technology that moves money from a payer to a payee. In India, every such system needs authorisation from the Reserve Bank of India (RBI) under the Payment and Settlement Systems (PSS) Act, 2007.
- PSS Act, 2007 — makes RBI the designated authority for payment systems; oversight is exercised through the Board for Regulation and Supervision of Payment and Settlement Systems (BPSS), a committee of the RBI Central Board.
- NPCI (National Payments Corporation of India) — set up in 2008 as an umbrella retail-payments organisation promoted by RBI and the Indian Banks’ Association; a not-for-profit (Section 8) company. It runs UPI, IMPS, RuPay, NACH, AePS and FASTag (NETC).
- UPI (Unified Payments Interface) — launched by NPCI in April 2016, built on the IMPS rails. It links multiple bank accounts to one app through a Virtual Payment Address (VPA) and settles 24×7 in real time.
- P2P vs P2M — Person-to-Person transfers move money between individuals; Person-to-Merchant payments are made to a business. P2PM is NPCI’s category for small merchants (such as street vendors) who accept payments on a personal-style QR.
What is MDR? The Merchant Discount Rate is the fee a merchant (not the customer) pays on each digital payment it receives. It is shared among the acquiring bank, the issuing bank, the payment app / PSP and the network. Card MDRs have long existed; UPI’s MDR was set to zero.
Lineage — How UPI Became Free, and Why That Is Now Changing
- Union Budget, July 2019 — announced that businesses with turnover above ₹50 crore must offer low-cost digital modes with no MDR on either customer or merchant.
- 1 January 2020 — zero MDR took effect for UPI and RuPay debit cards, given legal force through Section 10A of the PSS Act (inserted by the Finance (No. 2) Act, 2019) read with the income-tax provision on prescribed electronic modes.
- August 2022 — RBI released a Discussion Paper on Charges in Payment Systems, asking whether UPI should carry a tiered charge. The Government then said it was not considering any charge on UPI.
- April 2023 — NPCI allowed an interchange of up to 1.1% on merchant payments above ₹2,000 made from prepaid wallets (PPIs) over UPI. Bank-account-to-merchant UPI remained free.
- Incentive schemes — to compensate banks for zero MDR, the Union Cabinet approved budgetary incentives for RuPay debit and low-value BHIM-UPI P2M payments, including ₹2,600 crore for 2022-23 and ₹1,500 crore for 2024-25 (the latter for payments up to ₹2,000 to small merchants).
- September 2026 — the new framework, notified under the PSS Act, 2007 after deliberations of the UPI Steering Committee, introduces a limited MDR on higher-value merchant payments.
▤ Framework at a Glance
- Statutory basis: Payment and Settlement Systems Act, 2007; rates settled by the UPI Steering Committee.
- Nodal Ministry: Ministry of Finance (Department of Financial Services); operator — NPCI; regulator — RBI.
- Always free: all P2P transfers of any amount — no transaction fee, platform fee or other charge on individuals.
- No MDR: P2M payments up to ₹2,000; and all receipts of small merchants under P2PM receiving up to ₹1 lakh per month via UPI QR.
- General MDR: 0.4% on P2M payments above ₹2,000, capped at ₹300 per transaction (the cap binds from ₹75,000).
- Essential & thin-margin sectors: flat ₹5 per transaction above ₹2,000 — railways, telecom, insurance, fuel, agricultural inputs.
- Capital markets: 0.02%, capped at ₹300 — mutual funds, securities, stockbrokers and dealers.
- Customer protection: banks advised to stop merchants passing MDR to customers; UPI apps prohibited from platform fees or hidden charges; no monthly quotas on free use.
- Small-merchant fund: 5% of total MDR collections to a dedicated fund for UPI adoption among small merchants.
- Coverage estimate: about 96% of P2M transactions unaffected; P2P accounts for about 70% of UPI value (Government estimates).
Figure 1 — Who Pays What: The New UPI Charging Tree
The charge sits only on the right-most branch — higher-value payments to merchants that are not small P2PM vendors.
Working the Numbers — What a Merchant Actually Pays
Because the 0.4% rate is capped at ₹300, the effective rate falls for very large tickets. A ₹2,00,000 payment attracts ₹300, not ₹800 — an effective rate of 0.15%. The figures below are computed directly from the notified rates.
Figure 2 — MDR Payable on a General P2M Payment (₹)
The ₹300 cap makes the charge regressive in reverse — the largest merchant tickets pay the lowest effective rate.
Why It Matters
- Viability of Digital Public Infrastructure (DPI): zero MDR left banks and apps with no direct revenue from UPI, making ecosystem costs — fraud control, uptime, rural acceptance — dependent on budgetary incentives.
- Fiscal angle: a merchant-side fee on larger payments shifts part of the cost from the Union Budget to the users best able to bear it.
- Inclusion protected by design: the free tiers cover individuals, micro-enterprises and street vendors — the groups whose adoption drove UPI’s growth.
- Sectoral calibration: a flat ₹5 for thin-margin sectors and 0.02% for capital markets show an attempt to avoid distorting essential services and retail investment.
- Parliamentary input: the Government states the framework is consistent with the Standing Committee on Finance’s 32nd Report, which stressed a viable revenue model.
The Critical View
- Count vs value: 4% of P2M transactions by number may be a much larger share by value, because only high-ticket payments are charged. The revenue base is concentrated in fewer, bigger merchants.
- Pass-through risk: banks are only “advised” to stop merchants surcharging customers. Enforcement against hidden price loading will be difficult to monitor across millions of outlets.
- Transaction-splitting and category gaming: a ₹2,000 threshold invites splitting of bills, and the zero-MDR P2PM category may be used by merchants who are not genuinely small.
- Legal consistency: the zero-MDR mandate rests on Section 10A of the PSS Act; the instrument reconciling the new charge with that mandate needs clear public notification.
- Market concentration: MDR revenue shared with apps may reward the largest third-party apps. NPCI’s proposed 30% volume cap per app, first announced in November 2020, has seen its compliance deadline extended repeatedly.
- Behavioural shift: some high-value merchants may nudge buyers back to cash or to other instruments, working against the less-cash objective.
◈ Institutions & Terms — Prelims Hooks
- Interchange fee — the part of a payment fee paid by the acquiring bank to the issuing bank; MDR is the broader fee paid by the merchant.
- PSP (Payment Service Provider) bank — a bank that connects a Third-Party App Provider (TPAP) to UPI; apps cannot connect to NPCI directly.
- UPI Lite (2022) — on-device wallet for small-value payments without a bank-server call; UPI123Pay (2022) — UPI for feature phones.
- RuPay credit cards on UPI — permitted from 2022; credit lines on UPI followed in 2023.
- Payments Infrastructure Development Fund (PIDF) — RBI’s fund (from 2021) to deploy acceptance infrastructure in Tier-3 to Tier-6 centres; a useful comparison for the new 5% small-merchant fund.
✎ Mains Practice Question
“Zero MDR helped UPI achieve mass adoption but left its operators without a sustainable revenue model.” Critically examine whether a calibrated merchant discount rate can balance the sustainability of digital public infrastructure with the goal of financial inclusion. 15 marks · 250 words
02
Varuna Elevated Corridor — An Elevated Highway Along a River in One of India’s Oldest Living Cities
A 43.218-km, ₹10,998-crore elevated highway will run along the Varuna river to link NH-31 with the Varanasi Ring Road — testing how India adds road capacity to a dense heritage city without widening its historic lanes.
◈ Static Background — From the Basics
- The city’s name: Varanasi is traditionally derived from two tributaries of the Ganga — the Varuna on its northern side and the Assi on its southern side. It is also known as Kashi and Banaras.
- Setting: the city lies on the western (left) bank of the Ganga, where the river flows northward (Uttaravahini) — one reason for its ghats-facing-east orientation and religious significance.
- Constitutional basis of highways: highways declared by Parliament to be national highways are in Entry 23, Union List (Seventh Schedule); they are declared under the National Highways Act, 1956.
- NHAI: constituted under the National Highways Authority of India Act, 1988, operational from 1995; it is the implementing agency under MoRTH.
- PM Gati Shakti National Master Plan — launched in October 2021, a GIS-based platform integrating infrastructure planning across ministries; complemented by the National Logistics Policy (September 2022).
- Heritage law: the Ancient Monuments and Archaeological Sites and Remains (AMASR) Act, 1958, as amended in 2010, bars new construction within a 100-m prohibited area and regulates it within a further 200-m regulated area around centrally protected monuments.
▤ Project at a Glance
- Total cost: ₹10,998 crore; the release itemises ₹4,565.33 crore for civil construction and ₹934.91 crore for land acquisition — together ₹5,500.24 crore; the balance is not broken down.
- Length & design: 43.218 km, predominantly elevated 6/4-lane, with flyovers, loops, ramps and service roads; design speed 80–100 km/h.
- Approving authority: Union Cabinet, July 2026.
- Implementing agency: NHAI under the Ministry of Road Transport & Highways.
- Alignment: along the Varuna river, linking NH-31 with the Varanasi Ring Road; part of the Varanasi Decongestion Plan.
- Signature structures: an iconic cable-stayed bridge and an extradosed foot-over-bridge-cum-major bridge.
- Connectivity nodes: Lal Bahadur Shastri International Airport, Varanasi Cantonment, Varanasi City and Kashi stations, Deen Dayal Upadhyaya Junction, Ramnagar port, the Chandauli Socio-Economic Zone and six logistics nodes.
- Stated outcomes: NH-31 to Kashi station cut from about 40 to 20 minutes; Varanasi Junction to the airport from nearly an hour to about 20 minutes (government projections).
₹10,998 cr
Sanctioned cost
43.218 km
Corridor length
80–100
Design speed (km/h)
6/4-lane
Mostly elevated
Figure 3 — Projected Travel Time (minutes)
Both routes are projected to fall to about 20 minutes — outcomes to be tested once the corridor opens.
From the Basics — Three Ways to Build a Bridge
The corridor combines two bridge forms. A cable-stayed bridge hangs its deck directly from tall pylons through straight cables. An extradosed bridge is a hybrid: short pylons carry cables at a shallow angle that act like external prestressing for a stiff girder deck.
Figure 4 — Girder vs Extradosed vs Cable-Stayed (schematic)
Extradosed designs sit between girder and cable-stayed bridges — useful where pylon height must be kept low, such as near heritage skylines or flight paths.
Lineage & Linkages
- Bharatmala Pariyojana (Phase-I, approved October 2017) — the umbrella highway programme under which many ring roads, bypasses and economic corridors were planned.
- Varanasi Ring Road — built to divert through traffic around the city; the corridor now links it with NH-31 through the city along the Varuna.
- Ramnagar multimodal terminal on National Waterway-1 (Ganga) — inaugurated in November 2018 under the World Bank-assisted Jal Marg Vikas Project; road access decides whether such river terminals attract cargo.
- Deen Dayal Upadhyaya Junction (formerly Mughalsarai, renamed 2018) in Chandauli — a major rail hub on the Eastern Dedicated Freight Corridor alignment.
- Kashi Vishwanath Corridor (inaugurated December 2021) — has raised pilgrim footfall, sharpening the city’s peak-season congestion.
The Critical View
- River and floodplain: piers in or beside the Varuna channel can affect flood flow and sediment. Floodplain regulation under the River Ganga (Rejuvenation, Protection and Management) Authorities Order, 2016 and environmental scrutiny will matter, as the Varuna is already a polluted tributary.
- Induced demand: transport research repeatedly finds that new urban road capacity attracts more traffic; without public transport and parking policy, time savings can erode.
- Heritage skyline: elevated structures near ghats or protected sites need AMASR Act clearances and heritage impact assessment, and change the visual character of a historic city.
- Cost transparency: only about half of the ₹10,998-crore cost is itemised in the release; the implementation mode (EPC, HAM or BOT) is also not stated.
- Rehabilitation: land acquisition along a dense river corridor must follow the RFCTLARR Act, 2013, including Social Impact Assessment for affected residents and informal settlements.
✎ Mains Practice Question
Infrastructure in India’s historic cities must reconcile mobility, heritage conservation and river ecology. Discuss the challenges involved, with reference to elevated road corridors in heritage cities, and suggest safeguards. 15 marks · 250 words
Science & TechnologyGeneral Studies Paper III
03
SEMICON India 2026 and the Semiconductor Mission — How a Chip Works, and Where India Stands in the Value Chain
SEMICON India 2026 opens at Yashobhoomi, Dwarka (New Delhi) on 17 September under the theme “Silicon to Systems: Building the Ecosystem” — two months after the Cabinet approved Semicon 2.0 with a ₹1,27,500-crore outlay.
◈ Static Background — Part A: What Is a Semiconductor?
Materials are classed by how easily electrons move through them. Conductors (copper, aluminium) carry current freely; insulators (glass, silicon dioxide) almost block it. Semiconductors — chiefly silicon (Si) — lie in between, and their conductivity can be precisely controlled.
- Band theory: electrons in a solid occupy energy ranges called bands. The filled valence band and the higher conduction band are separated by a band gap (Eg). An electron must gain at least Eg of energy to conduct.
- Typical band gaps: germanium ≈ 0.66 eV, silicon ≈ 1.12 eV, gallium arsenide ≈ 1.42 eV, silicon carbide ≈ 3.2 eV, gallium nitride ≈ 3.4 eV; insulators such as SiO2 ≈ 9 eV.
- Temperature behaviour: a semiconductor’s resistance falls as temperature rises (more electrons cross the gap) — the reverse of metals, whose resistance rises with heat.
- Wide-bandgap (compound) semiconductors like SiC and GaN tolerate high voltage, heat and frequency — used in EV power electronics, fast chargers, 5G and radar.
Figure 5 — Conductor, Semiconductor and Insulator: The Band-Gap Picture
The size of the band gap decides whether a material conducts, blocks, or — like silicon — can be switched between the two.
◈ Static Background — Part B: Doping, Junctions and the Transistor
- Intrinsic vs extrinsic: pure silicon is intrinsic and conducts poorly. Adding tiny, controlled impurities — doping — makes it extrinsic.
- n-type: doped with pentavalent atoms (phosphorus, arsenic, antimony) — extra electrons are the majority carriers; the dopants are called donors.
- p-type: doped with trivalent atoms (boron, aluminium, gallium, indium) — holes (missing electrons) are the majority carriers; the dopants are acceptors.
- p–n junction: joining p- and n-regions creates a depletion region that lets current flow easily in one direction only — the basis of the diode, LED and solar cell.
- Transistor: a switch or amplifier with no moving parts — invented at Bell Labs in 1947 (Bardeen, Brattain, Shockley; Nobel Prize 1956). The integrated circuit followed in 1958–59 (Jack Kilby, Robert Noyce).
- MOSFET (Metal–Oxide–Semiconductor Field-Effect Transistor) — demonstrated at Bell Labs in 1959 (Mohamed Atalla, Dawon Kahng); today the most manufactured device in history and the building block of every digital chip.
How a MOSFET Switches — Reading the Band Diagram
At the heart of a MOSFET is a MOS capacitor: a metal gate, a thin insulator (oxide), and a doped silicon body. Applying a gate voltage (V) does not push current through the insulator — it bends the energy bands in the silicon beneath it.
Figure 6 — MOS Capacitor: Depletion (top) and Inversion (bottom)
Left: conduction (green) and valence (red) edges bend near the insulator as gate voltage V rises. Right: charge on each side of the insulator.
Image supplied for this analysis — a standard MOS-capacitor band diagram; reproduced for educational use.
- Top panel — depletion: a modest positive gate voltage on a p-type body repels mobile holes from the surface. What remains is a layer of fixed, negatively charged acceptor ions (−QA), balanced by charge Q = QA on the gate. The bands bend only slightly.
- Bottom panel — inversion: at a higher voltage the bands bend so far that the conduction-band edge approaches the electron energy level at the surface. A thin sheet of mobile electrons (Qn) forms right at the interface; the gate charge becomes Q = Qn + QA.
- Why this matters: that electron sheet is the inversion layer — a conducting channel. Add n+ source and drain regions on either side and the MOS capacitor becomes a MOSFET.
- The switch: below the threshold voltage (VT) there is no channel — OFF (0); above VT the channel conducts — ON (1). Billions of such switches make up a processor.
- Why the oxide must be thin: a thinner insulator gives the gate stronger control, but too thin lets electrons tunnel through. Industry therefore moved from SiO2 to high-k dielectrics (hafnium-based) from the 45-nm era onward.
◈ Static Background — Part C: Nodes, Moore’s Law and Lithography
- Moore’s Law (1965) — Gordon Moore’s observation that transistor counts on a chip double roughly every two years (revised in 1975); it is an industry trend, not a physical law.
- Process “node” (e.g. 28 nm, 3 nm): once the physical gate length; today largely a generation label. Smaller nodes pack more transistors, use less power and cost far more to build.
- Transistor architecture: planar → FinFET (mass production from 22 nm, 2011) → Gate-All-Around (GAA) at 3 nm and 2 nm, where the gate wraps the channel on all sides.
- Photolithography prints circuit patterns with light. Advanced nodes need Extreme Ultraviolet (EUV) light at 13.5 nm; mature nodes use Deep UV (193 nm). The Netherlands’ ASML is the sole supplier of EUV scanners.
- Mature vs leading-edge: 28 nm and above (mature nodes) still serve automobiles, power management, defence and IoT — the segment most of India’s first projects target.
Figure 7 — The Semiconductor Value Chain
India entered the chain at the easiest end — systems assembly — and is now working backwards into packaging, fabrication and equipment.
Lineage — India’s Long Road to a Fab
- Semi-Conductor Complex Ltd (SCL), Mohali — a public-sector fab incorporated in 1976, producing from 1984; a fire in 1989 set back India’s early lead. It survives as a mature-node facility used for strategic and academic chips.
- Special Incentive Package Scheme (SIPS), 2007 — offered capital subsidies for fabs; attracted proposals but no fab was built.
- 2013–14 — two fab consortia received in-principle approval (Jaiprakash Associates–IBM–TowerJazz and HSMC–STMicroelectronics–Silterra); both lapsed for want of finance and demand certainty.
- National Policy on Electronics: 2012 → 2019 — NPE 2019 set a target of US$400 billion of electronics manufacturing by 2025.
- 2020 — PLI Scheme for Large-Scale Electronics Manufacturing, SPECS and EMC 2.0 — pulled global mobile assembly into India.
- December 2021 — Semicon India Programme (₹76,000 crore) and the India Semiconductor Mission (ISM), an independent business division within Digital India Corporation under MeitY.
- July 2026 — Semicon 2.0 (₹1,27,500 crore) approved, built on six pillars.
▤ Mission at a Glance
- Semicon 1.0 outlay: ₹76,000 crore (approved 2021) — fabs, display fabs, compound semiconductors, ATMP/OSAT, and the Design Linked Incentive (DLI) scheme.
- Support model (1.0): fiscal support of up to 50% of project cost on a pari-passu basis for fabs and packaging units, often topped up by State incentives.
- Semicon 2.0 outlay: ₹1,27,500 crore, approved by the Union Cabinet in July 2026.
- Six pillars of 2.0: chip design, equipment & materials, fabrication, advanced packaging, R&D, talent.
- Nodal body: India Semiconductor Mission, Ministry of Electronics & IT.
- Projects: 12 approved across six States, investment commitments above ₹1.64 lakh crore; spanning silicon and compound fabs, display fabrication and advanced packaging.
- Status: three facilities in commercial production (as stated by the Government).
- Talent target: 85,000 skilled semiconductor engineers within the decade (government target).
The Electronics Base — Assembly as the Proof of Concept
The Government presents the growth of electronics and mobile manufacturing since 2014-15 as the foundation for chipmaking. The figures below are as stated in the backgrounder; they measure gross output, not domestic value addition.
Figure 8 — Electronics Output and Exports (₹ lakh crore), 2014-15 vs 2025-26
The steepest multiples are in mobile exports, which started from a near-zero base — a reminder to read growth multiples against base values.
- Smartphones were, per the Government, India’s largest single exported commodity in FY 2025-26, ahead of petroleum products and gems & jewellery.
- India is the second-largest mobile phone manufacturer by volume; the Government states that 99.2% of phones used in India are made domestically and that the sector supports about 2.5 million jobs.
Building the Talent Pipeline
- Chips to Startup (C2S) Programme — EDA tools deployed in 320 academic institutions; over 68,000 students trained.
- Design Linked Incentive (DLI) Scheme — 24 chip-design projects approved for support; 105 start-ups and MSMEs given EDA tool access.
- Tape-outs: by April 2026, 211 chips taped out by 75 institutions; seven fabricated, at nodes down to 12 nm. A tape-out is the final design sent for fabrication.
- ChipIN Centre at C-DAC — a centralised national facility for design tools, fabrication access and training; used by over 1 lakh engineers from 500+ organisations, with 300+ designs sent for fabrication at SCL Mohali and foreign foundries.
The Geopolitics of Chips — Pax Silica and the Global Subsidy Race
The COVID-19 chip shortage idled car plants worldwide and exposed how concentrated production is. Taiwan’s TSMC earns roughly two-thirds of global foundry revenue, and ASML alone makes EUV scanners. Governments responded with industrial policy on a scale not seen in decades.
- Pax Silica — a US-led supply-chain coalition launched in December 2025 to secure the full “silicon stack”, from critical minerals and fabrication to AI systems. India joined during the India AI Impact Summit, February 2026.
- United States: CHIPS and Science Act, 2022 — about US$52.7 billion for domestic chip manufacturing, research and workforce.
- European Union: European Chips Act, 2023 — aims to double the EU’s global production share to 20% by 2030.
- Japan: subsidies for TSMC’s Kumamoto fab and the Rapidus 2-nm project in Hokkaido.
- India–US track: the iCET (2022–23), relaunched as TRUST in 2025, covers semiconductors and critical minerals; India is also a member of the Wassenaar Arrangement (since 2017), relevant to dual-use technology controls.
▤ SEMICON India — Event Facts
- Organisers: SEMI (global industry association for the electronics supply chain) with the India Semiconductor Mission.
- Past editions: 2022 Bengaluru, 2023 Gandhinagar, 2024 Greater Noida, 2025 New Delhi.
- 2026 edition: Yashobhoomi (IICC), Dwarka; three days from 17 September; theme “Silicon to Systems: Building the Ecosystem”.
- Scale: 600+ exhibitors, 300 international companies, 15,000 sq m, 150+ speakers, six country and 12 State pavilions, a start-up showcase, student hackathon, workforce pavilion and women’s forum.
The Critical View
- Fab economics: fabs are among the most capital-intensive plants in industry and become outdated quickly. With up to half the cost met by the Centre and more by States, the subsidy per job is very high and returns depend on sustained utilisation.
- Mature-node focus: India’s first fabs target 28 nm and above — strategically useful, but a crowded market where China is rapidly adding capacity, raising price-competition risks.
- Import dependence persists: equipment, speciality gases, chemicals and wafers are largely imported; the equipment & materials pillar of Semicon 2.0 addresses the gap that earlier schemes left.
- Resource intensity: fabs need uninterrupted power and large volumes of ultra-pure water — a concern in water-stressed States such as Gujarat, where several units are located.
- Assembly ≠ value addition: the electronics boom rests largely on final assembly of imported components; the NPE 2019 target of US$400 billion by 2025 was not met.
- Talent quality: training counts show reach, but fab-floor process engineers and equipment technicians — skills built only through years of production — remain scarce.
- Alignment risk: membership of US-led coalitions can bring technology access but also export-control obligations that may constrain trade choices; India’s traditional strategic autonomy must be balanced.
◈ Terms to Know — Prelims Hooks
- Fabless — designs chips without owning a fab; Foundry — manufactures chips designed by others; IDM (Integrated Device Manufacturer) — does both.
- OSAT — Outsourced Semiconductor Assembly and Test; ATMP — Assembly, Testing, Marking and Packaging.
- EDA — Electronic Design Automation software used to design and verify chips.
- Wafer — thin disc of ultra-pure silicon (today up to 300 mm) on which chips are made; die — one chip cut from it.
- Advanced packaging — stacking or tightly linking multiple dies (chiplets, 2.5D/3D) to raise performance without shrinking the node.
- SoC — System-on-Chip, integrating processor, memory controllers and other functions on one die.
✎ Mains Practice Question
India has moved from electronics assembly towards semiconductor manufacturing, yet a self-reliant chip ecosystem requires far more than fabrication plants. Examine the progress made under the India Semiconductor Mission and identify the gaps that the next phase must address. 15 marks · 250 words
Legacy IAS Academy · Daily PIB Analysis
16 September 2026 · Press Information Bureau
